1. Field of the Invention
The present invention relates to an electrophotographic printer, and more particularly to an electrophotographic printer having a smoothing circuit for smoothing slant portions of characters and figures on the basis of modulated video signals to enhance image quality.
2. Description of Related Art
As a technique on a smoothing circuit in a conventional electrophotographic printer have been known Japanese Laid-open Patent Application No. Hei-2-112966 entitled "IMAGE OUTPUTTING METHOD AND DEVICE" and U.S. Pat. No. 4,847,641 entitled "PIECE-WISE PRINTIMAGE ENHANCEMENT FOR DOT MATRIX PRINTER" which were filed by and patented to Hewlett-Packard Company, Japanese Laid-open Patent Application No. Hei-3-33769 entitled "OPTICAL RECORDING DEVICE" filed by Hitachi, Ltd., and Japanese Laid-open Patent Application No. Hei-5-6438 entitled "METHOD FOR CORRECTING PICTURES DISPLAYED BY PRINT DEVICE OR DISPLAY DEVICE AND DEVICE FOR CORRECTING OUTPUT OF PRINT DEVICE AND DISPLAY DEVICE FOR PRODUCING DIGITALIZED PICTURES IN DOT MATRIX FORMAT" and U.S. Pat. No. 5,029,108 entitled "EDGE ENHANCEMENT METHOD AND APPARATUS FOR DOT MATRIX DEVICES" which have been filed by and patented to Destiny Technology Corporation.
Further, there have been also known Japanese Laid-open Patent Application No. Hei-4-268867 entitled "INFORMATION RECORDING DEVICE", Japanese Laid-open Patent Application No. Hei-4-341060 entitled "INFORMATION RECORDING DEVICE" and Japanese Laid-open Patent Application No. Hei-6-992 entitled "RECORDING DEVICE" which were filed by Canon Inc., Japanese Laid-open Patent Application No. Hei-4-304070 entitled "IMAGE PROCESSING DEVICE" filed by Ricoh Co., Ltd., Japanese Patent Application No. Hei-5-500443 entitled "RASTER PRINT DRIVING DEVICE" and U.S. Pat. No. 5,109,283 entitled "RASTER SCANNING ENGINE DRIVER WHICH INDEPENDENTLY LOCATES ENGINE DRIVE SIGNAL TRANSISTORS WITHIN EACH CELL AREA" which were filed by Xerographic Laser Images Corporation".
According to the Japanese Laid-open Patent application No. Hei-2-112966 and U.S. Pat. No. 4,847,641, as shown in FIG. 98, there are provided an FIFO buffer 550 for outputting a sampling window formed of 49 cells containing the center cell which are selected from a subset 11 bits.times.7 lines formed by inputting a bit map image, a piecewise matching network for inputting the sampling window to compare plural preset templates, and a compensation sub cell generator 552 for replacing the center cell of the sampling window by a compensation sub cell and outputting it if the sampling window is coincident with any template or directly outputting the center cell as it is if the sampling window is coincident with no template. The setting of the templates and the detection of the coincidence in the piecewise network 551 are performed by a programmable logic array (PLA). Generation of a compensation sub cell in the compensation sub cell generator 552 is performed with a clock whose period is equal to eight times of the period of the ordinary video output, and the compensation sub cell generator 552 generates eight kinds of compensation sub cells in accordance with the kind of the coincident template.
According to the Japanese Laid-open Patent Application No. Hei-3-33769, as show in FIGS. 99 and 100, there are provided a buffer memory 560 which has a memory capacity of four lines and is adapted to store pixel data corresponding to pixels to be recorded and pixel data around the pixel data concerned within a predetermined range from input pixel data of a host computer, a pattern recognition device 561 for recognizing on the basis of the stored pixel data what kind of image the pixel data corresponding to the recording image quality belongs to as a pixel, and outputting a recognition result as recognition data, a data base 562 for storing a light exposure pattern signal on a photosensitive member of an engine so that the recording pixel can be most ideally recorded, and selecting a light exposure pattern signal on the basis of recognition data, and a current converter 563 for converting the light exposure pattern signal to a driving current for the engine. The pattern recognition in the pattern recognition device 561 and the definition of the light exposure pattern signal to the recognition data in the data base 562 are performed by a memory 564 in which a value of five pixels in longitudinal direction and five pixels in lateral direction is set as an address. The generation of the driving current in the current converter 563 is performed by shifting and outputting the light exposure pattern signal with a clock having four times of the period of ordinary video output by shift registers 565, and then generating current values of four levels per bit with a transistor.
According to the Japanese Laid-open Patent Application No. Hei-5-6438 and U.S. Pat. No. 5,029,108, as shown in FIG. 101, there are provided an FIFO 570 which has a capacity of seven lines and is adapted to temporarily store input video picture data to assign a predetermined bit location as TBAP (to-be-adjusted-pixel), a gradient mask edge detector 571 for detecting an edge segment on the basis of a convolution of a 3.times.3 pattern matrix containing the TBAP at the center thereof and a 3.times.3 gradient mask matrix and classifying the bit pattern matrixes into either a horizontal or vertical group on the basis of the direction of gradient change indicated by the result of the convolution while previously-evaluated pixels and yet-to-be-evaluated pixels are contained, a segment change detector 572 for comparing the vertical and horizontal groups with vertical and horizontal sets of reference bit patterns to judge necessity of correction of TBAP, and generating a specific internal code when the necessity is judged, an address generator 573 for converting the internal code to an address code, a lookup table 574 for receiving the address code and outputting a modulation instruction code, and a modulator 575 for outputting a video signal which is modulated by the modulation instruction signal. The generation of the video signal modulated in the modulator 575 is performed by forward and reverse clocks of eight times of the period of the ordinary video output.
According to the Japanese Laid-open patent Application No. Hei-6-992, as shown in FIGS. 102 and 103, there are provided a line memory 580 which is input with an image signal VDO with a clock signal VCLK and adapted to store dot information of nine lines, a shift register 581 for forming dot matrix data of 11 dots in the main scanning direction and 9 lines in the auxiliary scanning direction on the basis of the output of the line memory 580, a processing circuit 582 for detecting the feature of the dot matrix data to change a pixel being noted (hereinafter referred to as "target pixel") 5f if occasion demands, and outputting a parallel signal MDT of 4 bits and light amount indication codes L1 to L3 of 3 bits indicating the irradiation intensity of each bit, a clock generating circuit 583 for generating a clock signal which is synchronized with a main operating synchronous signal BD and has the frequency of four times of the ordinary output period, a frequency-dividing circuit 583 for quartering the clock signal VCK to generate a clock signal VCKN, and a parallel/serial converter 585 for converting a parallel signal MDT to a serial signal VDOM on the basis of the clock signal VCK.
The feature detection of the target pixel in the processing circuit 582 is performed by a logic circuit which is adapted to detect a boundary line in the neighborhood of the target pixel by collation with predetermined patterns from reference areas of 11.times.9, a logic circuit for detecting the coincidence of pixels of each of seventeen divided small areas, and a logic circuit for determining the value of the parallel signal MDT and the light amount indication code in accordance with a combination condition of the above detection results. The generation of the driving current of a laser diode is performed by generating current values of 8 levels per bit on the basis of the serial signal VDOM and the light amount indication codes L1 to L3 by constant current switching circuits 586.
According to the Japanese Laid-open patent application No. Hei-4-304070, as shown in FIG. 104, there are provided an FIFO buffer 590 for storing binary image data supplied from a page memory for three(n) lines and supplied the data in m(dot).times.n(line) area with a notice picture, a comparison pattern unit 591 for storing comparison patterns each comprising 3 pixels.times.3 pixels, an enlargement processor 592 for comparing the comparison patterns and image data of a 3.times.3 area which contain a target pixel at the center thereof and are supplied from the FIFO buffer 590, and performing 2.times.2-enlargement processing to enlarging the target pixel by 2.times.2 times in accordance with the comparison result, a line buffer 593 which has a capacity of two lines and is adapted to store data which are enlarged by 2.times.2 times, and a filter processor 594 for performing spatial filtering processing of 2.times.2 areas and converting the enlarged image to multivalue data. The multivalue data generated in the filter processor 594 are supplied to a laser printer having a multivalue laser driver.
According to the Japanese Laid-open Patent Application No. Hei-5-500443 and U.S. Pat. No. 5,109,283, as shown in FIG. 105, there are provided a software 600 which operates on a host computer and severs to control the overall print driving device, a line data storage unit 601 for temporarily storing image information input from the host computer, a timing controller 602 for generating necessary timing signal and control signal in response to a horizontal synchronous signal and a vertical synchronous signal of an engine, a lookup table 603 for outputting a digital signal indicating the position of a transition point of an output picture signal in a basic print cell while a data signal transmitted from the line data storage unit 601 is used aa an address, and a modulation circuit 604 for outputting the transition modulation signal to the engine in accordance with the digital signal.
The image information input from the host computer comprises a binary image whose resolution is two times as high as that of the engine in both horizontal and vertical directions, or a multivalue image whose resolution is equal to that of the engine. With respect to the binary image, a pixel array of 4 pixels in the horizontal direction and 4 pixels in the vertical direction is set as a basic print cell, and it is used as an address for the lookup table 603. With respect to the multivalue image, a pixel array of 2 pixels in the horizontal direction and 2 pixels in the vertical direction is set as a basic print cell, and the value of each pixel and the position information are set as an address for the lookup table 603. A synchronizing circuit for generating a basic double clock signal in the timing controller 602 comprises a selection circuit 605, a delay circuit 606, a priority encoder 608, etc. as shown in FIG. 106. The modulation circuit 604 is achieved by an analog circuit comprising a D/A converter, an analog/ramp generator, a comparator and a coupler. Further, in place of the timing controller 602 and the modulation circuit 604, a digital picture signal modulation circuit which comprises a digital circuit may be used.
The conventional electrophotographic printers as described above have the following problems.
First, in the Japanese Laid-open Patent Application No. Hei-2-112966 and the U.S. Pat. No. 4,847,641, since the templates are empirically-derived bit patterns representing composite error elements which are common to all the bit map images, tests and estimations are required for various images every engine in order to design the templates and establish the association between each template and each compensation sub cell, and an application to each individual device is not easy. Further, since the compensation sub cell is generated with the clock based on an ordinary oscillator, the variation point of the compensation sub cell becomes rough when the transmission rate of the video signal is high, and thus the optimum compensation sub cell cannot be generated, so that the best image quality cannot be obtained. In addition, an FIFO buffer having a capacity enough to store pixels of eight lines is needed, resulting in cost-up.
In the Japanese Laid-open Patent Application No. Hei-3-33769, calculations and recording tests are required for various images every engine in order to design recognition data and establish the association between each recognition data and a light exposure pattern signal, and thus an application to each individual device is not easy. Further, the engine is required to be a multivalue laser printer having a representation capability of 4-level gray scale and this technique is not applicable to a general binary laser printer. Further, the driving current to the engine is merely varied at 4-division/4-level per output pixel, and synchronization based on the clock signal of four times increases jitter in the horizontal direction, so that the best image quality cannot be obtained. In addition, a buffer memory having a capacity enough to store pixels of four lines and a memory having a 25-bit address space for generating the light exposure pattern signal are needed, resulting in cost-up.
In the Japanese Laid-open Patent Application NO. Hei-5-6438 and the U.S. Pat. No. 5,029,108, a slight improvement is made from the viewpoint of the direction of the gradient change of a 3.times.3 area having a target pixel at the center thereof. However, no clear definition is provided to the design of the reference bit pattern and the establishment of the connection (association) between each detection result and the address code, and this definition must be prepared every device. Therefore, the application of this technique to an individual device is not easily performed. Further, since the modulated video signal is generated by the clock based on the ordinary oscillator, the variation point of the video signal becomes rough when the transmission rate of the video signal is high, so that the optimum video signal cannot be generated and thus the best image quality cannot be achieved. In addition, since an FIFO having a capacity enough to store pixels of seven lines, the cost is increased.
In the Japanese Laid-open Patent Application No. Hei-6-992, Japanese Laid-open Patent Application No. Hei-4-341060 and the Japanese Laid-open Patent Application No. Hei-4-268867, an improvement is acknowledged from the viewpoint of the support of the binary half-tone images. However, the association between the result of the feature detection of the target pixel and the output signal to the engine in the processing circuit is fixed in the circuit, and this circuit must be designed and prepared every device. Therefore, the application to an individual device cannot be easily preformed. Further, a multivalue laser printer having a representation capability of 8-level gray scale must be used as the engine, and thus this technique is not applicable to a general binary laser printer. Still further, the driving current to the engine is merely varied at 4-division/8-level per output pixel, and the synchronization based on the clock signal of four times increases the jitter in the horizontal direction, so that the best image quality cannot be obtained. In addition, a line memory having a capacity enough to store pixels of 9 lines is needed, so that the cost is increased.
In the Japanese Laid-open Patent Application No. Hei-4-304070, since the scale of enlargement in the enlargement processor is fixed, there are some input images for which the contours of the enlarged images cannot be smoothed. Further, since the multivalue data generated in the filter processor is disposed at the center of print pixels, the contour of the output image cannot be aligned, and thus the best image quality cannot be obtained. Still further, this technique is used on the assumption that a multivalue laser printer is used, and it is not applicable to a general binary laser printer. In addition, a line buffer is needed to hold an enlarged image, and thus the cost must be increased.
In the Japanese Laid-open Patent Application No. Hei-5-500443 and the U.S. Pat. No. 5,109,283, an image to be generated is a binary image having two-times resolution in the horizontal and vertical directions or a multivalue image of 8 bits. Therefore, in the case of the binary image, a memory capacity and a processing capability of four times are needed. In the case of the multivalue image, a memory capacity and a processing capability of eight times are needed. Therefore, this technique causes the cost to increase remarkably. Further, in the case of the binary image, the frequency of the maximum transition in the basic print cell of input four pixels is equal to 2, and thus a larger amount of information may be lost as compared with an ordinary print mode. On the other hand, since the transition modulation signal is generated with plural clock signals using a delay circuit, this technique may be applied even when the transmission rate of the video signal is high, and the jitter in the horizontal direction can be minimized. However, the delay circuit is constructed by an LCR time-constant circuit or a one-shot multivibrator. Not only does the characteristic of each of these constituent elements of the delay circuit have a large dispersion, but also the characteristic itself is greatly varied with variation of temperature and applied voltage. Therefore, a user must provide an observing means and an adjusting means for the delay characteristic, and must adjust the delay characteristic to his desired characteristic by using these means at all times.